Title:
半導体記憶装置及びその製造方法
Document Type and Number:
Japanese Patent JP4751169
Kind Code:
B2
Abstract:
To provide a semiconductor memory device where a NAND cell unit is built on a partial SOI substrate and its manufacturing method.
This semiconductor memory device consists of a semiconductor substrate, a semiconductor layer which has been formed on the above semiconductor substrate via an insulating film and has been made contact to the above semiconductor substrate via an opening created on the above insulating film, a number of electrically rewritable non-volatile memory cells which have been formed on the above semiconductor substrate and have been connected in series, and a NAND cell unit with a first selective gate transistor and a second selective gate transistor placed at both ends.
COPYRIGHT: (C)2007,JPO&INPIT
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Inventors:
Riichiro Shirata
Fumitaka Arai
Toshiyuki Toda
Hiroyoshi Tanimoto
Naoki Kusunoki
Nobutoshi Aoki
Makoto Mizukami
Fumitaka Arai
Toshiyuki Toda
Hiroyoshi Tanimoto
Naoki Kusunoki
Nobutoshi Aoki
Makoto Mizukami
Application Number:
JP2005301906A
Publication Date:
August 17, 2011
Filing Date:
October 17, 2005
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2004221500A | ||||
| JP2005252268A | ||||
| JP11163303A | ||||
| JP8316335A | ||||
| JP2000277707A |
Foreign References:
| WO1996042112A1 |
Attorney, Agent or Firm:
Masaru Itami
Kazuhiko Tamura
Kazuhiko Tamura