Title:
半導体集積回路及びその設計装置
Document Type and Number:
Japanese Patent JP4751216
Kind Code:
B2
Abstract:
A semiconductor integrated circuit contains a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates a pattern to be input to said logic circuit, a pattern compactor which receives data output from said logic circuit that has received the pattern, compacts the data, and outputs a result, and a logic built-in self test control unit which controls operations of said pattern generator and said pattern compactor and controls an operation of causing a scan path in said logic circuit to shift upon receiving the pattern; a device circuit which operates upon receiving the clock; and a device circuit built-in self test circuit which executes a built-in self test of said device circuit.
Inventors:
Kenichi Azusa
Tokunaga Chikako
Satoshi Hasegawa
Tokunaga Chikako
Satoshi Hasegawa
Application Number:
JP2006065503A
Publication Date:
August 17, 2011
Filing Date:
March 10, 2006
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP2003208331A | ||||
| JP2001289908A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki