Title:
半導体装置
Document Type and Number:
Japanese Patent JP4755405
Kind Code:
B2
Abstract:
There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate 109 ; a P-type annular well 181 provided in the element formation surface side of the P-type Si substrate 109 ; and a N-type annular well 183 provided inside the P-type annular well 181 . Moreover, an SRAM-P-type well 185 and an SRAM-N-type well 189 are provided inside the N-type annular well 183 . A deep N-type well 133 is provided nearer to the bottom side of the P-type Si substrate 109 than the SRAM-P-type well 185 and the SRAM-N-type well 189 . A plurality of P-type wells 103 are provided outside the P-type annular well 181 , and a N-type 101 is provided in such a way that the well 101 encloses the outside faces of the P-type wells 103.
Inventors:
Masuoka
Application Number:
JP2004299245A
Publication Date:
August 24, 2011
Filing Date:
October 13, 2004
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L27/092; H01L21/822; H01L21/8238; H01L27/04
Domestic Patent References:
| JP11289060A | ||||
| JP2003100904A | ||||
| JP2004253499A | ||||
| JP2001339046A |
Attorney, Agent or Firm:
Shinji Hayami