Title:
MRAM装置
Document Type and Number:
Japanese Patent JP4758554
Kind Code:
B2
Abstract:
Resistance of a selected memory cell (12) in a Magnetic Random Access Memory ("MRAM") device (8) is sensed by a read circuit (20) including a differential amplifier (34), a first current mode preamplifier (38) coupled to a sense node (S0) of the differential amplifier (34), and a second current mode preamplifier (42) coupled to a reference node (R0) of the differential amplifier (34). During a read operation, the first preamplifier (38) applies a regulated voltage to the selected memory cell (12), and the second preamplifier (42) applies a regulated voltage to a reference cell (26). A sense current flows through the selected memory cell (12) and to the sense node (S0) of the differential amplifier (34), while a reference current flows through the reference cell (26) and to the reference node (R0) of the differential amplifier (34). Resulting is a differential voltage across sense and reference nodes (S0 and R0). The differential voltage indicates whether a logic value of '0' or '1' is stored in the selected memory cell (12).
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Inventors:
Frederick A. Perner
Kenneth I Eldredge
Lang Ti Trang
Kenneth I Eldredge
Lang Ti Trang
Application Number:
JP2001028596A
Publication Date:
August 31, 2011
Filing Date:
February 05, 2001
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/14; G11C11/15; H01L21/8246; H01L27/105; H01L43/08
Domestic Patent References:
| JP6342598A | ||||
| JP61292293A | ||||
| JP11306785A | ||||
| JP2000163950A | ||||
| JP1271996A |
Foreign References:
| WO2000060600A1 |
Attorney, Agent or Firm:
Mikio Hatta
Yasuo Nara
Katsuyuki Utani
Yasuo Nara
Katsuyuki Utani