Title:
カラムアドレスバッファ装置
Document Type and Number:
Japanese Patent JP4767462
Kind Code:
B2
Abstract:
There is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the column address buffering circuit generates specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto. Such an arrangement synchronizes the generation time of the specific internal address signals with those of other internal address signals by positioning a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled.
Inventors:
Atsushi Atsushi
Application Number:
JP2001395450A
Publication Date:
September 07, 2011
Filing Date:
December 26, 2001
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/407; G11C11/408; G11C11/4076; G11C11/413; G11C11/4093; G11C11/417
Domestic Patent References:
| JP2000076866A | ||||
| JP7045075A | ||||
| JP2000113669A | ||||
| JP2000357392A |
Attorney, Agent or Firm:
Kyosei International Patent Office