Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4772429
Kind Code:
B2
Abstract:
A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.
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Inventors:
Naoaki Sudo
Koji Kanamori
Kazuhiko Sanada
Koji Kanamori
Kazuhiko Sanada
Application Number:
JP2005248286A
Publication Date:
September 14, 2011
Filing Date:
August 29, 2005
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2005051227A | ||||
| JP2004152924A |
Attorney, Agent or Firm:
Kato Asamichi