Title:
半導体メモリ、メモリシステムおよびメモリシステムの動作方法
Document Type and Number:
Japanese Patent JP4772546
Kind Code:
B2
Abstract:
A memory system includes a semiconductor memory having a plurality of banks; and a controller accessing the semiconductor memory. The number of the banks is larger than the number of banks simultaneously accessed. When receiving an access command for the bank currently executing the access operation, the semiconductor memory activates a busy signal and keeps the busy signal active until the access operation currently executed is completed. The controller stops outputting a next access command while receiving the activated busy signal. Based on the received busy signal, the controller judges whether or not the next access command should be outputted to the semiconductor memory. Consequently, it is possible to easily execute the random access in a semiconductor memory having a plurality of banks, without giving any load to the system side, which can improve the data transfer rate at the time of the random access.
Inventors:
Toshiya Uchida
Application Number:
JP2006074533A
Publication Date:
September 14, 2011
Filing Date:
March 17, 2006
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G11C11/401; G06F12/06; G11C11/407
Domestic Patent References:
| JP58137182A | ||||
| JP6187237A | ||||
| JP10275463A | ||||
| JP2002109879A | ||||
| JP5174576A | ||||
| JP11283364A |
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori
Toshihide Mori