Title:
インタリーバメモリ及びデインタリーバメモリのためのアドレス生成装置
Document Type and Number:
Japanese Patent JP4777971
Kind Code:
B2
Abstract:
Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a fraction of the address fragments generated, which potentially will exceed a maximum allowable value, is compared to the maximum allowable value. If the compared address fragment exceeds the maximum allowable value it is discarded. If the compared address fragment does not exceed the maximum allowable value it is accepted.
Inventors:
Bergmann, Anders
Application Number:
JP2007502238A
Publication Date:
September 21, 2011
Filing Date:
March 03, 2005
Export Citation:
Assignee:
Telefon Akti Bora Get Elm Ericson (Pubble)
International Classes:
H03M13/27; G06F11/10; G06F12/14
Domestic Patent References:
| JP2004129240A | 2004-04-22 | |||
| JP2002532939A | 2002-10-02 | |||
| JP2002540712A | 2002-11-26 | |||
| JP2002541711A | 2002-12-03 | |||
| JP2003224479A | 2003-08-08 |
Attorney, Agent or Firm:
Miaki Kametani
Tetsuo Kanamoto
Koji Hagiwara
Tetsuo Kanamoto
Koji Hagiwara