Title:
半導体メモリ素子
Document Type and Number:
Japanese Patent JP4783002
Kind Code:
B2
Abstract:
A semiconductor memory element that stores data as a resistance difference. The memory element comprises a MIS transistor, a two-terminal variable resistor element, and a fixed resistor element. The MIS transistor has a gate. The two-terminal variable resistor element is connected between the gate of the MIS transistor and a first power-supply terminal. The variable resistor element has a resistance that changes in accordance with a current flowing in the variable resistor element or the direction in which the current flows and that remains unchanged when the current is made to stop flowing. The fixed resistor element is connected between the gate of the MIS transistor and a second power-supply terminal.
Inventors:
Shinichi Yasuda
Application Number:
JP2004326812A
Publication Date:
September 28, 2011
Filing Date:
November 10, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/10; H01L27/105; H01L43/08
Domestic Patent References:
| JP2004213860A | ||||
| JP2004311015A | ||||
| JP2001237388A | ||||
| JP2000306377A | ||||
| JP2002329842A | ||||
| JP2001273758A |
Attorney, Agent or Firm:
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto