To provide a nonvolatile semiconductor memory device where a gate length of a nonvolatile semiconductor memory cell is shortened to raise integration degree.

The width in gate length direction of a gate electrode 18 in a memory cell is less than a half of a cell pitch C which is the length form the center of a source line connect 31 to the center of a drain contact 32. The line thickness of the gate electrode 18 and an ONO film is reduced down to, for example, 0.5 F by thinning after formation of design rule F. The ratio of the gate length against the reduced oxide film effective gate insulating film thickness is around less than 10.

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