Title:
半導体装置
Document Type and Number:
Japanese Patent JP4786756
Kind Code:
B1
Abstract:
According to one embodiment, a semiconductor device includes a base layer on which a revision signal transmission circuit is formed, three or more interconnect layers laminated on the base layer, a power source interconnect or a ground interconnect on an uppermost interconnect layer, and a revision signal line which connects the revision control circuit only to the power source interconnect or the ground interconnect of the uppermost interconnect layer.
Inventors:
Kenichi Ishii
Application Number:
JP2010094186A
Publication Date:
October 05, 2011
Filing Date:
April 15, 2010
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/82; H01L21/3205; H01L21/822; H01L23/52; H01L27/04
Domestic Patent References:
| JP2009070850A | ||||
| JP2005116902A | ||||
| JP2005175208A | ||||
| JP11145396A |
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen