Title:
表示装置
Document Type and Number:
Japanese Patent JP4787395
Kind Code:
B2
Abstract:
An object is to eliminate the effect of jitter in a sampling clock to realize proper sampling of a video signal. An A/D converter (1) samples a video signal in synchronization with a sampling clock (VCLK) at a rate of a period which is ½ times the video period. The phase of the sampling clock (VCLK) is corrected in a phase correcting circuit (9). The sampled signals are held alternately as data (DL) and (DR) in two latches (14) (15). A data switching portion (16) selects output signals from one of the two latches (14) and (15). A calculating portion (21) calculates an absolute difference value (DeltaD) between the data (DL) and (DR) in each video period. A calculating portion (22) calculates a maximum value (Dmax) among the absolute difference values (DeltaD) in one frame. A phrase control portion (19) controls the phase correcting circuit (9) and the data switching portion (16) so that a video signal processing circuit (2) can receive sampled signals which are sampled signals which are sampled at a phase corresponding to the center of a rising transition which the maximum value (Dmax) makes as the phase varies.
Inventors:
Koichiro Hara
Yasuo Murakami
Yasuo Murakami
Application Number:
JP2000056715A
Publication Date:
October 05, 2011
Filing Date:
March 02, 2000
Export Citation:
Assignee:
NEC Display Solutions Co., Ltd.
International Classes:
G09G3/20; H03L7/07; G09G3/36; H03L7/081; H03L7/091; H04N5/06; H04N5/66; H04N5/12
Domestic Patent References:
| JP1157618A | ||||
| JP2260820A | ||||
| JP5249942A | ||||
| JP10340074A | ||||
| JP11046140A | ||||
| JP11177847A | ||||
| JP11194738A | ||||
| JP11219157A | ||||
| JP11282399A | ||||
| JP11298758A | ||||
| JP11338406A | ||||
| JP11355604A | ||||
| JP2000040963A |
Foreign References:
| WO1999042989A1 |
Attorney, Agent or Firm:
Sumio Tanai
Ryuichiro Mori
Naoki Matsuo
Ryuichiro Mori
Naoki Matsuo