Title:
遅延時間計測方法、遅延時間調整方法及び可変遅延回路
Document Type and Number:
Japanese Patent JP4809473
Kind Code:
B2
Abstract:
A variable delay circuit 1 includes: a multistage delay circuit 20 constructed by connecting delay elements D1 to Dn in series; a selecting unit 21 which selects one delayed signal obtained by introducing different amounts of delay by passing a reference clock through one or more of the delay elements D1 to Dn; a decision unit 23 which, at decision timing synchronized to the reference clock, makes a decision on the logic state of each delayed signal sequentially selected from among the plurality of delayed signals; and a changing point detection unit 24 which detects at least two delay elements Dm and Dk where a change has occurred in the logic state of the reference clock at the decision timing, and wherein the difference (k−m) between the numbers of delay elements through which the clock signal has passed until reaching one of the two detected delay elements Dm and Dk is used as the number of delay elements that provides a desired delay time.
Inventors:
Masazumi Maeda
Application Number:
JP2009508839A
Publication Date:
November 09, 2011
Filing Date:
March 30, 2007
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K5/135
Domestic Patent References:
| JP2003023343A | 2003-01-24 | |||
| JP2000059209A | 2000-02-25 | |||
| JPH1136757A | 1999-02-09 |
Attorney, Agent or Firm:
Atsushi Aoki
Koichi Itsubo
Higuchi Souji
Masami Enohara
Kurachi Yasuyuki
Ryu Kobayashi
Koichi Itsubo
Higuchi Souji
Masami Enohara
Kurachi Yasuyuki
Ryu Kobayashi