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Patent Searching and Data


Title:
半導体集積回路装置及び情報システム
Document Type and Number:
Japanese Patent JP4820632
Kind Code:
B2
Abstract:

To provide a semiconductor integrated circuit technology for reducing a leakage current by meticulously interrupting power of part of a function block in operations.

In the function block 1 including a clock tree, a combination circuit, flip-flops 7, 8, and a power switch 9, when clocks applied to the flip-flops 7, 8 are stopped, power of a part region 11 of the combination circuit and of a part circuit of the flip-flops 7, 8 is interrupted without losing contents of the flip-flops 7, 8. Using a signal resulting from processing a control signal of a higher-order side of the clock tree for a control signal of the power switch 9 can execute a wide variety of power controls for the combination circuit and the flip-flops 7, 8 while suppressing timing deterioration more in comparison with absence of the power control. When the clocks applied to the flip-flops 7, 8 are restarted, power is supplied to the part circuit of the combination circuit and the flip-flops 7, 8 and the operation is resumed.

COPYRIGHT: (C)2007,JPO&INPIT


Inventors:
Tetsuya Yamada
Yusuke Kanno
Application Number:
JP2005347856A
Publication Date:
November 24, 2011
Filing Date:
December 01, 2005
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
H03K19/00; G06F1/04; G06F1/32; H03K19/096
Domestic Patent References:
JP11003945A
JP2005065044A
JP2001117967A
JP2003330987A
JP2002329784A
JP2004253072A
Foreign References:
WO1999066640A1
Attorney, Agent or Firm:
Yamato Tsutsui