Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4824500
Kind Code:
B2
Abstract:
A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when overdriving begins, and is designed to supply voltage of power supply VDD1 to parallel-connected sense amplifiers. Capacitor C1 accumulates electrical charges referenced to in association with electrical charges supplied to sense the amplifiers via MOS transistor TP1. MOS transistor TP2 is turned on when overdriving begins, to supply voltage of power supply VDD1 to capacitor C1. The control circuit controls so that MOS transistors TP1, TP2 are turned off when the capacitor potential has reached voltage VREF1. There is also provided a MOS transistor turned on after the MOS transistors TP1, TP2 are turned off to supply a power supply voltage equal to the voltage VREF1 to the plural sense amplifiers.
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Inventors:
Shuichi Tsukada
Application Number:
JP2006214635A
Publication Date:
November 30, 2011
Filing Date:
August 07, 2006
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G11C11/4091
Domestic Patent References:
| JP8190437A | ||||
| JP562467A |
Attorney, Agent or Firm:
Kato Asamichi