Title:
半導体素子の製造方法
Document Type and Number:
Japanese Patent JP4873940
Kind Code:
B2
Abstract:
A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM cell and the flash memory cell are formed by using a first polysilicon layer; and a gate electrode of the logic device and control gates of the EEPROM cell and the flash memory cell are formed by using a second polysilicon layer. Thus, it is possible to stably form the logic device, the EEPROM cell and the flash memory cell in one chip.
More Like This:
| JP2015159319 | SEMICONDUCTOR DEVICE |
| JP3102475 | [Title of Invention] Tunnel element |
| JP2005302996 | MANUFACTURING METHOD OF FLASH MEMORY |
Inventors:
Zheng Yuu planting
Application Number:
JP2005354256A
Publication Date:
February 08, 2012
Filing Date:
December 08, 2005
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H01L27/115; H01L21/8247; H01L27/10; H01L29/788; H01L29/792
Domestic Patent References:
| JP2000243937A | ||||
| JP11111934A | ||||
| JP200216155A | ||||
| JP10189775A |
Foreign References:
| WO2004112139A1 |
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Kimio Matsumoto
Kakehi Yuro
Kimio Matsumoto