Title:
故障検出方法、試験回路及び半導体装置
Document Type and Number:
Japanese Patent JP4878936
Kind Code:
B2
Abstract:
A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part. The method judges if a fault exists in a second specific delay cell within the second delay part exists when testing the second specific delay cell, by detecting a second relative delay time between input and output signals of the second specific delay cell, and processing the second relative delay time at a timing based on an output of a delay cell within the first delay part.
Inventors:
Hiroaki Yamanaka
Application Number:
JP2006178476A
Publication Date:
February 15, 2012
Filing Date:
June 28, 2006
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G01R31/28; H01L21/822; H01L27/04; H03K5/14
Domestic Patent References:
| JP8008699A | ||||
| JP11101852A | ||||
| JP2002162441A | ||||
| JP2005322860A |
Attorney, Agent or Firm:
Tadahiko Ito