Title:
薄いゲート酸化膜用デカップリング・キャパシタ
Document Type and Number:
Japanese Patent JP4954413
Kind Code:
B2
Abstract:
In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
Inventors:
Keshavarji, Ali
De, Vivek Kay
Carnic, Tanay
Nair, Legend Run
De, Vivek Kay
Carnic, Tanay
Nair, Legend Run
Application Number:
JP2001547425A
Publication Date:
June 13, 2012
Filing Date:
November 13, 2000
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H01L27/04; H01L21/822; H01L27/08; H01L29/94
Domestic Patent References:
| JPH10163421A | 1998-06-19 | |||
| JPH0883887A | 1996-03-26 | |||
| JPH0513680A | 1993-01-22 | |||
| JPH10256489A | 1998-09-25 | |||
| JPH10107235A | 1998-04-24 |
Foreign References:
| US5883423A | 1999-03-16 | |||
| US5032892A | 1991-07-16 |
Attorney, Agent or Firm:
Masaki Yamakawa