Title:
少なくとも5面チャンネル型FINFETトランジスタの製造方法
Document Type and Number:
Japanese Patent JP4955214
Kind Code:
B2
Abstract:
An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.
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Inventors:
Lee Kasei
Tetsuji Ueno
Yanagi Jun
Lee Ho
Lee substitution
金 ▲ヒュン▼錫
Park Bunhan
Tetsuji Ueno
Yanagi Jun
Lee Ho
Lee substitution
金 ▲ヒュン▼錫
Park Bunhan
Application Number:
JP2005009650A
Publication Date:
June 20, 2012
Filing Date:
January 17, 2005
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L21/336; H01L29/78; H01L29/786
Domestic Patent References:
| JP2003243667A | ||||
| JP7086595A | ||||
| JP64061060A | ||||
| JP2014578A | ||||
| JP8139325A | ||||
| JP9321134A | ||||
| JP62042457A | ||||
| JP2001338988A | ||||
| JP4368180A |
Foreign References:
| WO2003003470A1 | ||||
| WO2003003442A1 | ||||
| US6475890 |
Other References:
W.Xiong et al.,Corner Effect in Multiple-Gate SOI MOSFETs,2003 IEEE International SOI Conference. Proceedings,2003年,pp.111-113
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro