Title:
プログラマブルデバイスに対するソフトエラーロケーションおよび感度検出
Document Type and Number:
Japanese Patent JP4960137
Kind Code:
B2
Abstract:
Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.
Inventors:
David Lewis
Nindy. Nugo
Andy L. Lee
Joseph fan
Nindy. Nugo
Andy L. Lee
Joseph fan
Application Number:
JP2007112429A
Publication Date:
June 27, 2012
Filing Date:
April 20, 2007
Export Citation:
Assignee:
Altera Corporation
International Classes:
G06F12/16; H03K19/177
Domestic Patent References:
| JP2006344223A | ||||
| JP200344366A | ||||
| JP200250957A | ||||
| JP2006519511A |
Foreign References:
| US6104211 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita