Title:
メモリの微小タイリングを行うメモリコントローラ、方法、及びシステム
Document Type and Number:
Japanese Patent JP4981797
Kind Code:
B2
Abstract:
According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
Inventors:
Akiyama, James
Clifford, William
Osborne, Randy
Clifford, William
Osborne, Randy
Application Number:
JP2008518483A
Publication Date:
July 25, 2012
Filing Date:
June 23, 2006
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/04; G06F12/02
Domestic Patent References:
| JP6095959A | ||||
| JP2002259327A | ||||
| JP8263367A |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation