Title:
設計を検証するシステム
Document Type and Number:
Japanese Patent JP5004566
Kind Code:
B2
Abstract:
A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation model using only the extracted resources, exclusive of an entire design, to test a specific function or group of interrelated functions represented by the discrete test case or set of associated test cases for design verification, and correlating the simulation results with the test plan.
Inventors:
Robert James Devins
Pascal A Same
David Wills Milton
Pascal A Same
David Wills Milton
Application Number:
JP2006317794A
Publication Date:
August 22, 2012
Filing Date:
November 24, 2006
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G01R31/28; G06F17/50
Domestic Patent References:
| JP8147344A | ||||
| JP2005222371A | ||||
| JP9293002A |
Foreign References:
| US20030191618 | ||||
| US20030154061 |
Other References:
A.M.Amendola, A.Benso, F.Corno, L.Impagliazzo, P.Marmo, P.Prinetto, M.Rebaudengo and M.Sonza Reorda,Fault Behavior Observation of a Microprocessor System through a VHDL Simulation-Based Injection Experiment,Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European,米国,1996年,536-541頁
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi