Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
マイクロローディング効果を軽減するためのSiGe埋め込みダミーパターンを備えたSiGe装置
Document Type and Number:
Japanese Patent JP5029469
Kind Code:
B2
Abstract:
A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.

More Like This:
JPH07120756[Title of the Invention] A method for manufacturing a semiconductor device
WO/2011/007470SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
JP7041653Semiconductor devices and their control methods
Inventors:
Lee Dongxing
Yang Myeongjong
Zheng Road
Kei Tadashi
Chang Zhang
Zhang Yudong
Application Number:
JP2008099955A
Publication Date:
September 19, 2012
Filing Date:
April 08, 2008
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MEDIATEK INC.
International Classes:
H01L29/78; H01L21/20; H01L21/336; H01L29/786
Domestic Patent References:
JP2000150806A
JP2007324589A
Foreign References:
WO2005106949A1
Attorney, Agent or Firm:
Akihiro Ryuka



 
Previous Patent: JPS5029468

Next Patent: プロンプター式操作装置