Title:
マクロ内端子配線を考慮したネットリストによって信号の遅延時間を予測する設計方法、及び、プログラム
Document Type and Number:
Japanese Patent JP5059657
Kind Code:
B2
Abstract:
A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block line connecting between the functional blocks, creating a third netlist by adding a second path information to the second netlist, the second path information corresponding to an intra-block line connected to a terminal of each functional block from inside of each functional block, creating a fourth netlist that models a line resistance and a line capacitance of an inter-instance line which combines the first path information and the second path information included in the third netlist, and estimating a delay time from information based on the fourth netlist.
Inventors:
Akihiro Asahina
Application Number:
JP2008047165A
Publication Date:
October 24, 2012
Filing Date:
February 28, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G06F17/50
Domestic Patent References:
| JP2006301837A | ||||
| JP2003296392A | ||||
| JP2001117960A |
Attorney, Agent or Firm:
Ken Ieiri