Title:
ソースレベルを追跡するためのワード線基準レベルの読み出し、ベリファイ
Document Type and Number:
Japanese Patent JP5086443
Kind Code:
B2
Abstract:
A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.
Inventors:
Bread phon
Femme, torun
Woo, Byunggi
Femme, torun
Woo, Byunggi
Application Number:
JP2010539684A
Publication Date:
November 28, 2012
Filing Date:
December 15, 2008
Export Citation:
Assignee:
SanDisk Technology Inc.
International Classes:
G11C16/06; G11C16/04
Domestic Patent References:
| JP2003524279A | ||||
| JP11096783A | ||||
| JP10149689A | ||||
| JP11066876A |
Foreign References:
| WO2006107706A1 |
Attorney, Agent or Firm:
Toshi Inoguchi