Title:
非同期式パイプラインのためのデータ・キャッシュ・ミスをアウト・オブ・オーダ方式で処理するための装置及び方法
Document Type and Number:
Japanese Patent JP5105887
Kind Code:
B2
Abstract:
Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to track the load instruction across multiple pipelines as an index into a load table data structure of a load target buffer. The load table is used to manage cache “hits” and “misses” and to aid in the recycling of data from the L2 cache. With cache misses, the LTAG indexed load table permits load data to recycle from the L2 cache in any order. When the load instruction issues and sees its corresponding entry in the load table marked as a “miss,” the effects of issuance of the load instruction are canceled and the load instruction is stored in the load table for future reissuing to the instruction pipeline when the required data is recycled.
Inventors:
Christopher Michael Abernathy
Ronald Hall
Jeffrey Powers Bradford
David Sippy
Timothy Hume Heil
Ronald Hall
Jeffrey Powers Bradford
David Sippy
Timothy Hume Heil
Application Number:
JP2007019199A
Publication Date:
December 26, 2012
Filing Date:
January 30, 2007
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F9/38; G06F12/08
Domestic Patent References:
| JP3201130A | ||||
| JP2003280896A | ||||
| JP11065928A | ||||
| JP64038834A | ||||
| JP2003131872A | ||||
| JP2002007209A | ||||
| JP2000515276A |
Foreign References:
| US20030061470 | ||||
| WO2001053951A1 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
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