Title:
半導体装置
Document Type and Number:
Japanese Patent JP5106666
Kind Code:
B2
Abstract:
An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.
Inventors:
Masayuki Sakakura
Shunpei Yamazaki
Shunpei Yamazaki
Application Number:
JP2011186226A
Publication Date:
December 26, 2012
Filing Date:
August 29, 2011
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G09F9/30; G02F1/1345; H01L21/336; H01L29/786; H01L51/50; H05B33/12; H05B33/14; H05B33/22; H05B33/26
Domestic Patent References:
| JP11133457A | ||||
| JP2004260133A | ||||
| JP2000122097A | ||||
| JP2005340011A | ||||
| JP2001125137A | ||||
| JP2000323698A | ||||
| JP2003338368A |
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