メモリ回路 - INTERNATIONAL BUSINESS MASCHINES CORPORATION

Title:

メモリ回路

Document Type and Number:

Japanese Patent JP5107550

Kind Code:

B2

Abstract:

A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.

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Inventors:

Robert Glenn Gerowitz
Kenichi Tsuchiya

Application Number:

JP2006272386A

Publication Date:

December 26, 2012

Filing Date:

October 04, 2006

Export Citation:

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Assignee:

INTERNATIONAL BUSINESS MASCHINES CORPORATION

International Classes:

G01R31/28; G11C29/12

Domestic Patent References:

JP7073699A
JP1162299A

Attorney, Agent or Firm:

Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi

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