Title:
重ねられた要素から成る微細構造の集合的な製作方法
Document Type and Number:
Japanese Patent JP5145593
Kind Code:
B2
Abstract:
The invention relates to the collective fabrication of superposed microstructures, such as an integrated circuit and a protective cover. Individual structures each comprising superposed first and second elements are fabricated collectively. The first elements (for example, integrated circuit chips) are prepared on a first plate and the second elements (for example, transparent covers) are prepared on a second plate. The plates are bonded to each other over the major portion of their facing surfaces, but with no bonding of the defined zones in which there is no adhesion. The individual structures are then diced via the top on the one hand and via the bottom on the other hand along different parallel dicing lines passing through the zones with no adhesion, so that, after dicing, the first elements retain surface portions (those lying between the parallel dicing lines) that are not covered by a second element. A connection pad may thus remain accessible at this point.
Inventors:
Philip Romvo
Bernard Aspearl
Bernard Aspearl
Application Number:
JP2007546026A
Publication Date:
February 20, 2013
Filing Date:
December 08, 2005
Export Citation:
Assignee:
Uduwe Semiconductors
Soitech Silicon on Insulator Technologies
Soitech Silicon on Insulator Technologies
International Classes:
H01L21/301
Domestic Patent References:
| JP2004207460A | ||||
| JP8316497A | ||||
| JP2003517946A | ||||
| JP2003523627A | ||||
| JP2000182915A | ||||
| JP2005528779A | ||||
| JP2002329851A | ||||
| JP2004006834A |
Foreign References:
| US6407381 | ||||
| WO2003105198A1 |
Attorney, Agent or Firm:
Takahisa Kimura