Title:
半導体装置
Document Type and Number:
Japanese Patent JP5190551
Kind Code:
B2
Abstract:
A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.
Inventors:
Teruyuki Fujii
Ryota Imabashi
Ryota Imabashi
Application Number:
JP2012165461A
Publication Date:
April 24, 2013
Filing Date:
July 26, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; G11C11/405; H01L21/768; H01L21/8234; H01L21/8242; H01L21/8247; H01L23/522; H01L27/06; H01L27/088; H01L27/10; H01L27/105; H01L27/108; H01L27/115; H01L27/146; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2010021170A | ||||
| JP2009141342A | ||||
| JP2009194351A | ||||
| JP2007027367A |