Title:
メモリ制御回路及び半導体装置
Document Type and Number:
Japanese Patent JP5200470
Kind Code:
B2
Abstract:
A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.
More Like This:
| JP2000021187 | SEMICONDUCTOR MEMORY APPARATUS |
| JPH06349287 | FLAG DATA MEMORY CIRCUIT |
Inventors:
Keisuke Nakanishi
Application Number:
JP2007243341A
Publication Date:
June 05, 2013
Filing Date:
September 20, 2007
Export Citation:
Assignee:
株式会社リコー
International Classes:
G11C16/06; G11C16/02; G11C29/00; G11C29/14
Domestic Patent References:
| JP2003110029A | ||||
| JP2006209489A | ||||
| JP2005020349A | ||||
| JP8204582A | ||||
| JP2007028898A | ||||
| JP8045281A |
Attorney, Agent or Firm:
Mitsuo Tanaka
Kyousei Tamura
Masahiro Ishino
Kyousei Tamura
Masahiro Ishino
Previous Patent: 溶接のスパーク検出方法及びスパーク検出装置ならびに溶接製品の製造方...
Next Patent: APPARATUS AND METHOD FOR ANGULAR ORIENTATION OF DISK
Next Patent: APPARATUS AND METHOD FOR ANGULAR ORIENTATION OF DISK