Title:
情報処理装置及びその制御方法
Document Type and Number:
Japanese Patent JP5201208
Kind Code:
B2
Abstract:
A clock adjustment circuit 1022-j (j=1 through N) delays a phase of a clock signal on the basis of a TAP value j so as to output an adjusted clock signal j. By synchronizing transmission data with the adjusted clock signal j, reception data j [1:0] is generated. A data adjustment circuit 1031-j delays the transmission data on the basis of a TAP2 value j. By synchronizing the delayed transmission data with the adjusted clock signal j, adjusted reception data j [1:0] is generated. A data adjustment control circuit 1035-j generates the TAP2 value j on the basis of a result of a comparison between the reception data j [1:0] and the adjusted reception data j [1:0], and outputs to a clock adjustment control circuit 1023-j an instruction to update the TAP value j.
Inventors:
Hiroshi Nakayama
Junji Ichinomiya
Shintaro Itozawa
Junji Ichinomiya
Shintaro Itozawa
Application Number:
JP2010515668A
Publication Date:
June 05, 2013
Filing Date:
June 03, 2008
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F13/42
Domestic Patent References:
| JPH1188309A | 1999-03-30 | |||
| JP2000163963A | 2000-06-16 | |||
| JP2000187642A | 2000-07-04 | |||
| JP2006209638A | 2006-08-10 |
Attorney, Agent or Firm:
Yoshiyuki Osuga
virtue Tamio Ei
virtue Tamio Ei