Title:
複数の狭区画レイアウトを用いたひずみデバイス及びその製造方法
Document Type and Number:
Japanese Patent JP5202941
Kind Code:
B2
Abstract:
A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.
Inventors:
Crello, giuseppe
Hoffman, Tomah
Armstrong, mark
Hoffman, Tomah
Armstrong, mark
Application Number:
JP2007506400A
Publication Date:
June 05, 2013
Filing Date:
March 25, 2005
Export Citation:
Assignee:
Intel Corporation
International Classes:
H01L21/336; H01L21/8234; H01L27/088; H01L29/06; H01L29/10; H01L29/78; H01L29/786
Domestic Patent References:
| JP2001185721A | ||||
| JP2001085691A | ||||
| JP2003060076A | ||||
| JP2004087640A | ||||
| JP2003273240A |
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito