Title:
デュアルゲート半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5203719
Kind Code:
B2
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Inventors:
Kadoshima Masaru
Application Number:
JP2008003140A
Publication Date:
June 05, 2013
Filing Date:
January 10, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8238; H01L27/092; H01L29/423; H01L29/49
Domestic Patent References:
| JP2001284466A | ||||
| JP2005093856A |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Haruo Nakano
Mitsuo Tanaka
Haruo Nakano