Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP5205066
Kind Code:
B2
Abstract:
The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.
Inventors:
Takeshi Furusawa
Takao Kamoshima
Ajiro Yuji
Takao Kamoshima
Ajiro Yuji
Application Number:
JP2008009023A
Publication Date:
June 05, 2013
Filing Date:
January 18, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/60; H01L21/3205; H01L21/768; H01L23/522
Domestic Patent References:
| JP2005286266A |
Attorney, Agent or Firm:
Yamato Tsutsui