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Title:
メモリシステム
Document Type and Number:
Japanese Patent JP5207434
Kind Code:
B2
Abstract:

To provide a technique capable of avoiding or reducing the risk of unintended rewriting of a data caused by reading repeatedly the data from a nonvolatile memory.

An access controller part 34 input with an operation switch request signal input from an address comparison part 33 switches an operation from a usual reading access to a normal read access, when a reading address output from a host system 1 in this time is consistent with a reading address output from a host system 1 in the last. That is, the access controller part 34 reading-accesses a memory buffer part 44, without read-access to a memory access array 43. The risk of unintended rewriting is thereby avoided or reduced by reading repeatedly the data stored in the memory access array 43.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
Takahiko Sugawara
Application Number:
JP2007054573A
Publication Date:
June 12, 2013
Filing Date:
March 05, 2007
Export Citation:
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Assignee:
Mega Chips Co., Ltd.
International Classes:
G06F12/00; G06F12/06; G06F12/16; G11C16/02
Domestic Patent References:
JP2001210073A
JP2001290791A
JP2006065384A
JP2008537618A
JP9293027A
Foreign References:
WO2006097726A1
Attorney, Agent or Firm:
Go Sakane



 
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