Title:
信号増幅装置
Document Type and Number:
Japanese Patent JP5270071
Kind Code:
B2
Abstract:
A signal amplification device which uses inexpensive standard CMOS and yet is capable of high-accuracy threshold setting. An offset voltage generator detects the direct-current level of an input signal, and generates a positive or negative offset voltage signal. A peak detector outputs, as a peak value, the positive offset voltage signal if the level thereof is higher than the maximum level of the input signal, or the maximum level of the input signal if the maximum level is higher than the positive offset voltage signal. A bottom detector outputs, as a bottom value, the negative offset voltage signal if the level thereof is lower than the minimum level of the input signal, or the minimum level of the input signal if the minimum level is lower than the negative offset voltage signal. A voltage divider subjects the peak and bottom values to voltage division, to generate a threshold level.
Inventors:
Satoshi Ide
Application Number:
JP2006136181A
Publication Date:
August 21, 2013
Filing Date:
May 16, 2006
Export Citation:
Assignee:
Fujitsu Optical Components Limited
International Classes:
H03K5/1532; H03F3/45; H03K5/153
Domestic Patent References:
| JP10261940A | ||||
| JP2000228623A |
Attorney, Agent or Firm:
Takeshi Hattori