Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP5292243
Kind Code:
B2
Abstract:
There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S2) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S6) and a predetermined linearity condition (S7).
Inventors:
Yasuyoshi Sunaga
Hideki Sakakibara
Yuko Ito
Nakamura Tomoji
Atsushi Hashiyama
Kozaburo Kurita
Kitsuda Tsutsuda
Hideki Sakakibara
Yuko Ito
Nakamura Tomoji
Atsushi Hashiyama
Kozaburo Kurita
Kitsuda Tsutsuda
Application Number:
JP2009221900A
Publication Date:
September 18, 2013
Filing Date:
September 28, 2009
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G01R31/316
Domestic Patent References:
| JP2001091587A | ||||
| JP2006294235A | ||||
| JP2006121615A | ||||
| JP7016183U | ||||
| JP2001094403A |
Foreign References:
| WO2008114307A1 |
Attorney, Agent or Firm:
Manabu Inoue
Yuji Toda
Yuji Toda