Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP5300658
Kind Code:
B2
Abstract:
To provide a semiconductor device capable of effectively reducing JFET resistance, and to provide a method of manufacturing the same.
An MOSFET includes: an n-type SiC drift layer 2 formed on an SiC substrate 1; a pair of p-type base regions 3 formed above the SiC drift layer 2; and an n-type high-concentration layer 9 formed at a depth of the bottom of the base region 3 over the SiC drift layer 2 and having a high impurity concentration than the SiC drift layer 2. The pair of base regions 3 each include a first base region 3a as an inner part of the pair of base regions 3, and a second base region 3b formed deeper than the first base region 3a outside it.
COPYRIGHT: (C)2011,JPO&INPIT
Inventors:
Keiko Sakai
Kenichi Otsuka
Shigehisa Miura
Kenichi Otsuka
Shigehisa Miura
Application Number:
JP2009195023A
Publication Date:
September 25, 2013
Filing Date:
August 26, 2009
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L29/78; H01L21/336; H01L21/337; H01L21/338; H01L29/12; H01L29/739; H01L29/808; H01L29/812
Domestic Patent References:
| JP2007184434A | ||||
| JP2006332232A | ||||
| JP2008503894A | ||||
| JP2006511961A | ||||
| JP2006332401A | ||||
| JP2001094097A |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita