To provide a method of designing a semiconductor integrated circuit, suppressing noises of a semiconductor integrated circuit and shortening a time required for designing.

A minimum cell arrangement interval determining section (arrangement prohibition region determining section) 13 determines the minimum cell arrangement interval between cells for each of cells on the basis of the average number of operations and use voltage per unit time of each cell, and also determines an arrangement prohibition region, and a cell arrangement section 14 arranges the cells so that they are not arranged in the arrangement prohibition region. In this way, a semiconductor integrated circuit for suppressing noises is designed, and a TAT (turnaround time) is shortened to reduce a period required for designing.

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