Title:
互い違いにされた論理アレイブロックのアーキテクチャ
Document Type and Number:
Japanese Patent JP5313531
Kind Code:
B2
Abstract:
A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second groups of LABs can be columns of LABs, and the columns can be vertically offset from each other (e.g., by half the number of logic elements in each LAB). The offsetting can advantageously allow more LABs to be reached using a single routing channel, or without using any routing channel, thereby reducing communication latency and improving overall IC performance.
Inventors:
David Cashman
Application Number:
JP2008074675A
Publication Date:
October 09, 2013
Filing Date:
March 21, 2008
Export Citation:
Assignee:
Altera Corporation
International Classes:
H03K19/177; H01L21/82
Domestic Patent References:
| JP5074935A | ||||
| JP64085421A | ||||
| JP2002538633A | ||||
| JP9219454A | ||||
| JP2003087112A |
Other References:
David Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David Galloway, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose,The Stratix II logic and routing architecture,Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays,米国,ACM,2005年 2月 6日,p14-20
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita