Title:
半導体装置
Document Type and Number:
Japanese Patent JP5315405
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize multiple pins and reduction of costs in a semiconductor device.SOLUTION: A semiconductor device comprises a microcomputer chip 3, an SDRAM 2 arranged beside the microcomputer chip 3 and thinner than the microcomputer chip 3, a tab 5c, a plurality of inner leads 5a and outer leads 5b, a first wire 6a connecting a pad of the microcomputer chip 3 and a pad of the SDRAM 2, and a second wire 6b which connects the pad of the microcomputer chip 3 and the inner lead 5a and is arranged beyond the SDRAM 2, and on which a loop is formed at a position higher than a loop of the first wire 6a. An interface circuit of a bus for a memory is closed in a package only for connecting chips without connecting to an external terminal, and therefore, pins conventionally used to connect to the external terminal can be used for other functions. Thus, multiple pins can be realized, and costs of SIP (semiconductor device) 1 can be reduced due to adoption of a frame type.
Inventors:
Fujio Ito
Suzuki Hiromichi
Akihiko Kameoka
Ken Sakamoto
Suzuki Hiromichi
Akihiko Kameoka
Ken Sakamoto
Application Number:
JP2011275802A
Publication Date:
October 16, 2013
Filing Date:
December 16, 2011
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L25/04; H01L21/60; H01L25/18
Domestic Patent References:
| JP11086546A | ||||
| JP2004053276A | ||||
| JP2004085526A | ||||
| JP2002076267A | ||||
| JP2000349226A | ||||
| JP2001274315A | ||||
| JP2004064008A | ||||
| JP2004079571A | ||||
| JP2000223657A |
Attorney, Agent or Firm:
Yamato Tsutsui