Title:
基準電流源回路
Document Type and Number:
Japanese Patent JP5323142
Kind Code:
B2
Abstract:
A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.
Inventors:
Tetsuya Hirose
Large saki
Large saki
Application Number:
JP2011157568A
Publication Date:
October 23, 2013
Filing Date:
July 19, 2011
Export Citation:
Assignee:
Semiconductor Science and Engineering Research Center Co., Ltd.
International Classes:
G05F3/26
Domestic Patent References:
| JP2008052639A | ||||
| JP7104876A | ||||
| JP9307370A | ||||
| JP2199517A | ||||
| JP10260082A | ||||
| JP2018606A | ||||
| JP2000181558A |
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Kawabata Junichi
Mitsuo Tanaka
Kawabata Junichi