Title:
昇圧回路
Document Type and Number:
Japanese Patent JP5336770
Kind Code:
B2
Abstract:
A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≰K≰M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented.
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Inventors:
Seiji Yamahira
Application Number:
JP2008140915A
Publication Date:
November 06, 2013
Filing Date:
May 29, 2008
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H02M3/07; G11C16/06; H01L21/822; H01L27/04
Foreign References:
| US7023260 |
Attorney, Agent or Firm:
Maeda patent office
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura