Title:
エラー検出・訂正符号生成回路及びその制御方法
Document Type and Number:
Japanese Patent JP5353655
Kind Code:
B2
Abstract:
An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log 2 (n+1) bits of one portion of a redundant portion of error detecting/correcting-code-attached data by rounding up the numbers to the right of the decimal point of log 2 (n+1) in response to the input of m bytes of an information portion included in error-detection-bit-attached data. The error-detection-bit-attached data includes a redundant portion of m bits of error detection bits allocated to the m bytes of the information portion, the byte having n bits. The circuit also includes a second exclusive OR operation circuit that generates m bits of another portion of the redundant portion of the error detecting/correcting-code-attached data in response to the input of the one portion and the error detection bits.
Inventors:
Shiro Kamoda
Application Number:
JP2009263229A
Publication Date:
November 27, 2013
Filing Date:
November 18, 2009
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03M13/19; G06F11/10; G06F12/16
Domestic Patent References:
| JP6324951A | ||||
| JP554775A | ||||
| JP5108495A |
Foreign References:
| US6675349 |
Attorney, Agent or Firm:
Tadahiko Ito
Akinori Yamaguchi
Akinori Yamaguchi