バリア膜とドレイン電極膜およびソース電極膜が高い密着強度を有する薄膜トランジスター

Title:

バリア膜とドレイン電極膜およびソース電極膜が高い密着強度を有する薄膜トランジスター

Document Type and Number:

Japanese Patent JP5360959

Kind Code:

B2

Abstract:

This thin-film transistor includes adhesive strength enhancing films between a barrier film and electrode films. Each of the adhesive strength enhancing film is composed of two zones including (a) a pure copper zone that is formed on the electrode film side, and (b) a component concentrated zone that is formed in an interface portion contact with the barrier film, and that includes Cu, Ca, oxygen, and Si as constituents. In concentration distributions of Ca and oxygen in a thickness direction of the component concentrated zone, a maximum content of Ca of a Ca-containing peak is in a range of 5 to 20 at %, and a maximum content of oxygen of an oxygen-containing peak is in a range of 30 to 50 at %, respectively.

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Inventors:

Satoru Mori
Shozo Omiyama

Application Number:

JP2008273728A

Publication Date:

December 04, 2013

Filing Date:

October 24, 2008

Export Citation:

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Assignee:

Mitsubishi Materials Corporation
ULVAC, Inc.

International Classes:

H01L29/786; H01L21/28; H01L29/417; H01L29/423; H01L29/49

Domestic Patent References:

JP2008205420A
JP2224254A
JP2001007204A
JP2007096241A

Foreign References:

WO2008081806A1

Attorney, Agent or Firm:

Kazuo Tomita
Kageyama Shuichi
Kageyama Shuichi

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