Title:
配線の作製方法
Document Type and Number:
Japanese Patent JP5371240
Kind Code:
B2
Abstract:
When a design diagram of the semiconductor device by a conventional CAD tool is used, a pattern which can be formed with the ink-jet apparatus is limited; therefore, there is a possibility that some circuits of the desired semiconductor device cannot be formed as they are designed. A plurality of basic patterns which can be obtained by discharging with the ink-jet apparatus are prepared, and layout of a desired integrated circuit is performed by combining the patterns. A light-exposure mask is formed based on the layout obtained. Light exposure is performed using the light-exposure mask. Then, development is performed, and the resist film remains in the light-exposed region of which width is narrower than the diameter of the droplet landed. Liquid repellent treatment is performed to an exposed portion on the surface, and then the material droplet is dropped over the resist film. Discharging is selectively performed by a droplet discharging method to form a wiring of which width is narrower than the dot diameter.
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Inventors:
Genki Fujii
Erika Takahashi
Erika Takahashi
Application Number:
JP2007331511A
Publication Date:
December 18, 2013
Filing Date:
December 25, 2007
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/3205; B05D1/26; G06K19/07; G06K19/077; H01L21/288; H01L21/336; H01L21/768; H01L21/82; H01L29/786; H05K3/10
Domestic Patent References:
| JP2005012179A | ||||
| JP2004080041A | ||||
| JP2001030478A | ||||
| JP2005103820A | ||||
| JP2002029097A | ||||
| JP2006196879A | ||||
| JP2007116119A |