Title:
出力回路及びそれを用いた受光回路、フォトカプラ
Document Type and Number:
Japanese Patent JP5385095
Kind Code:
B2
Abstract:
An output circuit includes a bias circuit that operates when a power supply voltage equal to or larger than a predetermined voltage is applied, a differential amplifier circuit that outputs signals according to input differential signals upon receiving a bias current or bias voltage generated when the bias circuit is operated, an output stage circuit that receives differential signals according to an output from the differential amplifier circuit and outputs output signals according to the differential signals, the output stage circuit having fewer number of stages of elements connected in series than the bias circuit, and a pull-down circuit that forcibly sets a level of one of the differential signals received by the output stage circuit to a ground voltage to fix the level of the output signals output from the output stage circuit when the bias current or the bias voltage generated by the bias circuit is not supplied.
Inventors:
Masafumi Shimizu
Satoshi Yoshimura
Satoshi Yoshimura
Application Number:
JP2009250107A
Publication Date:
January 08, 2014
Filing Date:
October 30, 2009
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03F1/00; H01L31/10; H01L31/12; H03F3/08
Domestic Patent References:
| JP3141711A | ||||
| JP2001203567A | ||||
| JP2009147800A | ||||
| JP9092874A | ||||
| JP2004328061A |
Attorney, Agent or Firm:
Ken Ieiri