Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP5390200
Kind Code:
B2
Abstract:
A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position.
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Inventors:
Shinobu Takehiro
Application Number:
JP2009008687A
Publication Date:
January 15, 2014
Filing Date:
January 19, 2009
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H01L21/8234; H01L27/088
Domestic Patent References:
| JP2004152806A | ||||
| JP2008507841A | ||||
| JP2007027440A | ||||
| JP5063202A | ||||
| JP2004042379A |
Attorney, Agent or Firm:
Motohiko Fujimura
Shigeyuki Nagaoka
Shinji Takano
Shigeyuki Nagaoka
Shinji Takano