Title:
画素回路、液晶装置及び電子機器
Document Type and Number:
Japanese Patent JP5391106
Kind Code:
B2
Abstract:
A pixel circuit that is connected with a scanning line and a data line includes a first transistor of which a gate electrode is connected with the scanning line and one of a source electrode and a drain electrode is connected with the data line, a second transistor of which a gate electrode is connected with the scanning line, one of a source electrode and a drain electrode is connected with the first transistor, and the other one of the source electrode and the drain electrode is connected with a first node, an auxiliary capacitor connected with a node at which the first transistor and the second transistor are connected to each other, a pixel electrode connected with the first node, a counter electrode opposed to the pixel electrode, liquid crystal held between the pixel electrode and the counter electrode, and a holding capacitor connected with the first node.
Inventors:
Shuji Ariga
Tokuo Booth
Hirosawa Koji
Tokuo Booth
Hirosawa Koji
Application Number:
JP2010039782A
Publication Date:
January 15, 2014
Filing Date:
February 25, 2010
Export Citation:
Assignee:
Japan Display Co., Ltd.
International Classes:
G02F1/1368; G02F1/133; G02F1/1343; G09G3/20; G09G3/36
Domestic Patent References:
| JP2002323707A | ||||
| JP5088644A | ||||
| JP8046204A | ||||
| JP4251818A |
Attorney, Agent or Firm:
Hiroaki Sakai
Jun Takamura
Takeshi Hattori
Jun Takamura
Takeshi Hattori